Job Description

Roles & Responsibilities

Your Mission

As an ASIC EDA Flow Specialist, you will be responsible for architecting, developing, and

maintaining the design flows and infrastructure that power our AI ASIC development. You will

partner closely with RTL, verification, physical design, and CAD engineers to build robust, scalable,

and efficient EDA environments that accelerate the path from RTL to silicon.

Your expertise will ensure our teams can innovate faster, with best-in-class automation, quality of

results, and time-to-tape-out.

Responsibilities

Develop, maintain, and optimize ASIC EDA flows across front-end, back-end, and sign-off

stages from RTL to GDS.

Manage EDA tool installations, updates, and license servers (FlexLM, RLM, SCL), including

license forecasting, allocation, and vendor coordination.

Oversee compute grid and storage infrastructure, ensuring optimal job scheduling, resource

utilization, and uptime for large-scale ASIC builds.

Architect and maintain Git-based infrastructure (GitLab) for design version control, CI/CD, and

team collaboration.

Manage and support IP vendor tools, including evaluation, installation, and maintenance of

vendor-specific environments (e.g., TSMC, ARM, Synopsys, Cadence).

Coordinate and track Soft and Hard IP integration within EDA flows, managing deliverables,

versioning, and quality checks.

Maintain a central IP database with metadata (version, PDK, constraints, verification status) to

streamline reuse across projects.

Collaborate with design teams to integrate third-party IPs into custom SoC flows and validate

tool/IP compatibility.

Automate repetitive setup tasks (e.g., IP import, constraint generation, regression setup,

reporting) to improve productivity.

Requirements

Ready to Accelerate the Future of AI?

If you’re passionate about building world-class design flows and enabling engineers to push the

limits of silicon performance, they would love to hear from you.

Develop and maintain dashboards for EDA tool usage, license consumption, and

compute/storage monitoring.

Document flow methodologies and provide internal training for new engineers.

Profile requirements:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

7 + years of experience in ASIC/SoC design environment management, CAD/EDA flow

development, or design infrastructure engineering.

Strong knowledge of EDA tools (Synopsys, Cadence, Siemens/Mentor) and their installation,

configuration, and licensing.

Experience with EDA license servers (FlexLM, RLM, SCL) and usage optimization.

Proficiency in Tcl, Python, Yaml, and Shell scripting for automation and flow development.

Proficiency in Make, CMake, or Bazel-based orchestration frameworks for flow and regression

builds.

Familiarity with compute grid management systems (LSF, SLURM, Grid Engine) and storage

architecture for large ASIC projects.

Practical experience with Git and integration into design workflows.

Proficiency in CI/CD automation, pipelines, or internal build systems.

Solid understanding of RTL-to-GDSII flow, timing/power trade-offs, and tool interactions.

Strong communication, documentation, and problem-solving skills.

Exposure to advanced process nodes (7 nm and below) and multi-die design methodologies.

ASIC EDA Flow Specialist
Client of MBR Partners

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