ASIC Verification Engineer
Client of MBR Partners
Employer Active
Posted 10 hrs ago
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Any Nationality
Gender
Not Mentioned
Vacancy
1 Vacancy
Job Description
Roles & Responsibilities
Responsibilities
You'll collaborate with Silicon architects (clarifying intent and performance targets), RTL designers (debug and ECOs), firmware and Linux driver teams (HW/SW co-verification), performance architects (workload traces
and counters), and EDA/CAD (flows, regressions, metrics) to ensure first-pass silicon success.
Own block-to-subsystem verification: author verification plans from specs, define stimulus/coverage strategy, and deliver sign-off with data (functional/code/assertion coverage).
Build scalable UVM environments: agents, monitors, scoreboards, sequences, reference models (C++/Python/DPI), protocol checkers, and reusable components.
Exercise real workloads: co-sim with firmware/drivers, run emulation/FPGA prototypes, and
correlate performance/behavior with architectural models.
Apply assertions & formal: write SVA, run formal where appropriate (protocol/liveness/safety),
and integrate results into overall coverage.
Close quality gates: lint/CDC/RDC verification collaboration, gate-level/reset/power-up scenarios, low-power (UPF) intent checks.
Harden regressions: own CI pipelines, randomized/constrained tests, triage failures, root-cause
with RTL/design, and track fixes to closure.
Interface & document: keep specs, test plans, coverage dashboards, and bug reports clear for
Architects, RTL, Firmware/Drivers, and DFT/PD teams.
Minimum requirements:
7+ years in ASIC/SoC verification with SystemVerilog/UVM (ownership from test plan to sign-
off).
Strong command of constrained-random stimulus, scoreboarding, coverage-driven
verification, and SVA.
Hands-on with major simulators (e.g., VCS/Questa/Xcelium) and regression/CI tooling.
Familiarity with standard protocols (AMBA, AXI, APB, AHB) and industrial VIPs
Experience verifying complex IP/subsystems (at least one of: multi-core compute, NoC/coherency, high-speed I/O like PCIe, Ethernet 100/400G, HBM/DDR, UCIe).
Proficient in scripting for automation (Python/TCL/Make) and building reusable verification
components.
Solid understanding of SoC fundamentals: resets, clocking, CDC/RDC, back-pressure/flow
control, performance counters.
Emulation/FPGA prototyping (Palladium/Zebu/Veloce; Xilinx/Intel) and SW-in-the-loop setups.
Formal verification experience (JasperGold/VC Formal) and assertion methodology leadership.
DFT/DFD awareness and post-silicon bring-up experience.
Exposure to AI accelerator domains (systolic/dataflow, memory hierarchies, tiling) and traffic
modeling.
Experience building coverage dashboards and integrating verification metrics into CI/CD.
Experience with C/C++/DPI for RTL Co-Simulation.
Send your application with links to UVM environments, papers, or examples of coverage
dashboards and debug write-ups. Show us how you design for finding the corner cases before
they find us.
Please ignore the salary levels mentioned here: the client is flexible depending on your profile.
Company Industry
Department / Functional Area
Keywords
- ASIC Verification Engineer
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Client of MBR Partners