Design Engineer

MBR Partners

You will collaborate closely with other designers in a high-impact environment to define the computational unit micro-architectural specifications and work alongside the architecture, physical design, and verification teams to identify potential issues.

Your role will involve implementing the micro-architecture, targeting advanced technology nodes while balancing energy efficiency, performance, and area constraints with project time-lines, maintainability, and code elegance.

You will also review synthesis and power reports, address timing and power issues, and ensure high-quality design standards. As the design nears functional completion, you will be collaborating with the verification team to confirm that the design behaves as intended and is thoroughly tested.

Additionally, you will be required to continue to liase and partner with the physical design team, assisting with any necessary adjustments to achieve an optimal layout.

Requirements

• 7+ years of experience in RTL design and ASIC development.
• Proficiency in RTL coding languages (Verilog/SystemVerilog)
• Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
• Experience writing specifications and converting them to design
• Experience with multiple clock domains and asynchronous interfaces
• Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable
• Experience in low-power design techniques such as clock- and power-gating is a plus
• Ability to communicate effectively across all internal groups
• Familiarity with scripting languages like Perl or Python or Tcl is a plus
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) is a plus