Senior Design Verification Engineer

EXALT Technologies

We are seeking motivated and experienced Design Verification Engineers to join our ASIC verification team.
You will work on complex, high-performance digital designs featuring PCIe, AXI, AHB, and Ethernet interfaces, using advanced SystemVerilog and UVM methodologies.

Key Responsibilities (Senior Level)

• Lead verification strategy and planning from specification to sign-off.
• Architect and develop advanced UVM testbenches.
• Define and maintain verification plans, identify corner cases, coverage goals, and sign-off criteria.
• Integrate and verify Verification IP (VIP) for standard interfaces such as PCIe, AXI, AHB, APB, and Ethernet (MAC/PHY).
• Write and execute SystemVerilog constrained-random and directed test scenarios for complex IP and SoC-level environments.
• Develop, track, and close coverage (functional, code, and assertion-based) to ensure full verification completeness.
• Implement assertion-based verification (SVA) and collaborate with formal verification teams for deeper validation.
• Debug and resolve complex issues using Mentor QuestaSim/Visualizer and Cadence Xcelium/SimVision, performing detailed root-cause analysis.
• Automate regression runs, build systems, and coverage reporting using Python, Perl, Tcl, or Shell scripting.

Bachelor s or Master s degree in Electrical or Computer Engineering (or equivalent).

• 3+ years of experience in Functional design verification.
• Strong background in SystemVerilog and UVM methodology.
• Hands-on experience with Mentor QuestaSim/Visualizer and/or Cadence Xcelium/SimVision.
• Solid understanding of digital design, synchronization, and timing concepts.
• Excellent debugging and problem-solving skills with complex SoC-level environments.
• Strong scripting and automation experience (Python, Perl, Shell).
• Excellent communication, documentation, and teamwork skills.