Showing 5

Uvm Jobs

ASIC Verification Engineer

Cisco Systems

Develop and upgrade test benches for ASIC verification, collaborate with teams, and ensure robust functionality through comprehensive testing and debugging.

30+ days ago
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Senior ASIC Verification Engineer

Cisco Systems

Develop and upgrade test benches, perform end-to-end verification, collaborate with teams, and possess expertise in System Verilog, UVM, and C++.

30+ days ago

ASIC Engineer

Cisco Systems

Develop and maintain advanced test benches using System Verilog and UVM, while collaborating on ASIC design verification and integration for multi-tenant cloud solutions.

21 Apr

Sr. Staff Pre-Silicon Validation/Verification Lead

Siemens AG

Lead verification and validation for high-speed interconnect protocols, develop scalable CI/CD pipelines, and mentor engineers in system-level testing.

17 Apr

ASIC Design

Develop and optimize ASIC design flows, lead digital design and verification, and integrate advanced EDA tools in a collaborative environment.

30+ days ago

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